In devices for detecting and/or locating cables or underground objects, a high selectivity in a narrow bandwidth is important in order to maximise instrument sensitivity. In digital signal processing, such selectivity can, in part, be obtained by using SINC filters. Such SINC filters are useful because they allow exact control of high frequencies, and predictable aliasing thereof. It is simple to arrange such SINC filters so that the aliased frequencies fall outside the bandwidth of a filter that computes at a down-sampled rate. Generally, a cascade of SINC filters, with nomenclature SINCn, where n is the number, or order, of cascaded SINC filters, is used in order to decimate, i.e. to reduce the rate of a signal from the sampling rate to a down-sampled rate. The ratio of sampling rate to down-sampled rate is called the decimation ratio.
Cable detection and location devices are generally portable devices, for use in a number of environments. Therefore, power consumption is an important factor in the design of such devices. Low power consumption allows the design to be more compact and allows for longer operating periods. Considerations in such power requirements include the power consumption of the data processing elements of the device. The simpler the processor that can be used, in general the lower the power requirements. Modern DSP architecture and semiconductor technology allow low cost 32 bit floating point devices with computational engines operating at 0.25 mW/MIP. 64 bit processors are also available; however, these have much higher power requirements and are generally unsuitable for low power applications.
Two available methods of calculating the frequency response of a SINCn filter in a Digital Signal Processor (DSP) are by use of modular arithmetic followed by a number of differentiators, and the use of recursive filtering. The first method involves modular arithmetic for the summing process and is followed by a number of differentiators, operating after the down-sampling stage, to reconvert the modular representation. In an example, such a modular arithmetic method, in order to accurately represent a cascade of 5 SINC filters, without unacceptable truncation, with a total decimation ratio of 240 would require a 72 bit accumulator. While the method is computationally efficient, it is not suitable for low computation implementation of a 5th order decimating filter on a 32 bit processor because of the need for a 72 bit accumulator.
The second method makes use of a cascade of Infinite Impulse Response (IIR) recursive filters. Such a filter gives a highly accurate representation of a SINCn. A simple difference equation can be used to determine the filter response for each stage of the filter:yn=yn−1+xn−xn−Nwhere yn is the current output of the filter; yn−1 is the previous output from the filter; xn is the current input to the filter; and Xn−N is the input to the filter delayed by N samples (where N is the decimation ratio).
Such a filter is, once again, computationally efficient. However, because the response is recursive, any errors in each value are compounded as the filter runs. Because any processor will have a limited accuracy, the recursion will cause truncation errors when the filter is run continuously. These truncation errors lead to gain instability in the filter. With a 32 bit processor these errors become too large for the IIR filter to be useful, as the accuracy of the processor is only 24 bit (24 bit mantissa, with 8 bit exponent).
Therefore, there is a need to improve the filter characteristics for representation of SINC decimating filters in the digital domain when used in devices for detecting and/or locating cables or other underground or otherwise inaccessible objects, in particular, when implemented on a low power processor, for example a 32 bit floating point processor.